To solve this challenge, avionics suppliers have been gravitating towards using a mixture of powerful
commercial-off-the-shelf (COTS) hardware platforms coupled with standards-based open virtualization
platforms to extract value across multiple product lines, aircraft, and use cases.
Wind River is a trusted partner that supports customers on their digital transformation path. Having the
highest levels of safety and security addressing the most challenging environments, Wind River’s
653 Multi-core Edition is now available on Arm® architecture. This allows customers to quickly
changing business needs and respond to the growing desire for innovation and workload consolidation at
fundamental levels, starting with the architecture upon which their safety-critical system is based.
With this latest release, Wind River brings its portfolio of safe and secure platforms to all the major
hardware architectures. Having already added support for VxWorks 653 on Intel architecture earlier this year
means that programs can save costs and accelerate time-to-market (TTM) by consolidating legacy and new
applications on the hardware platform of their choice, while providing a safe and secure software foundation
that is open, renders high levels of technology readiness and re-use, and lowers certification risks and
costs throughout the entire product lifecycle.
The next-generation avionics and industrial systems can now be built using a standards-based, open
virtualization platform capable of running multiple operating environments across Arm, Intel, and Power
processor architectures. VxWorks 653 is a certification-ready platform capable of abstracting and running
any type of workload, including legacy and new, with multiple levels of safety.
Why is Arm architecture support important?
VxWorks 653 has been tested and validated on the Arm® Cortex® A53 (Xilinx UltraScale + MPSoC). Arm-based
CPUs are found in both the edge computing and high-performance computing spaces, and Arm technology enables
mission critical applications to run at the desired performance levels in a low SWaP envelope and